Department of Electrical and Computer Engineering University of Texas at San Antonio One UTSA Circle, San Antonio, Texas, 78249, U. S. A.;
Department of Electrical and Computer Engineering University of Texas at San Antonio One UTSA Circle, San Antonio, Texas, 78249, U. S. A.;
Department of Electrical and Computer Engineering University of Texas at San Antonio One UTSA Circle, San Antonio, Texas, 78249, U. S. A.;
Department of Electrical and Computer Engineering University of Texas at San Antonio One UTSA Circle, San Antonio, Texas, 78249, U. S. A.;
leakage reduction; CMOS adders; static power;
机译:纳米CMOS VLSI系统的漏电降低技术及技术扩展对漏电功率的影响
机译:低泄漏功率的CMOS全加法器的VLSI实现
机译:降低泄漏功率的CMOS超前加法器的研究与分析
机译:漏洞 - 宽纳米级CMOS添加剂中的延迟折衷
机译:宽比特CMOS纳米加法器拓扑与应用的泄漏减少技术之间的性能折衷。
机译:接触塞沉积条件对多级CMOS逻辑互连器件中结漏电流和接触电阻的影响
机译:VLSI实现CMOS全加入者,具有低漏电