Fast chip-level static and transient thermal analysis method for thermal management of VLSI ICs in packages.

摘要

High-temperature and temperature non-uniformity in high-performance ICs are becoming increasingly important because thermal effects can significantly degrade chip performance and reliability. Due to the increasing trend of power density as technology advances, thermal consideration has become an inseparable aspect in VLSI chip design and verification. Thus accurate temperature information is a critical factor for thermal-aware design and verification.;Conventional grid-based methods such as finite element method (FEM) and finite difference method (FDM) are computationally expensive. In this study, we developed an accelerated temperature computation method, called Power Blurring (PB), to significantly enhance the computational efficiency in acquiring on-chip thermal profiles of VLSI ICs in packages. The PB method is implemented by blending the concept of Green's function method and image filtering. The most important component of the PB method is the thermal mask. The thermal mask is an impulse response (i.e. Green's function) to a point heat source applied to a full-chip thermal package. Once the thermal mask is obtained through finite element analysis (FEA), thermal profiles can be quickly obtained for any power dissipation map. To the Method of Image along with intrinsic error compensation was introduced. The PB method was applied to both static and transient thermal simulations. It produced thermal profiles with maximum error less than 3% for various case studies, reducing the computation time by two orders of magnitude, compared to a commercial FEA tool, ANSYS. The additional advantage of the PB method is that the thermal mask can be used for evaluation of different power dissipation profiles with no need to re-mesh the whole 3D structure. A thermal tester chip has been designed and fabricated for validation of the PB method. Very good agreements between simulation results and experiment results were observed.;The PB method was successfully applied to high spatial thermal simulations and vertically integrated IC (3D IC) thermal simulations. To mitigate the dependence on FEA, a methodology for parameterization of the thermal mask is also presented.