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A static random access memory cell based on a thin capacitively coupled thyristor device.

机译:基于薄电容耦合晶闸管器件的静态随机存取存储单元。

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摘要

During the past two decades, processing speeds have increased by three to four orders of magnitude while DRAM random access speed has increased by less than an order of magnitude. The huge gap between the speed of processors and memory can be addressed by faster technologies such as SRAM, but the use of conventional SRAM is limited by the fact that it is an order of magnitude less dense than DRAM. The processor-memory performance gap has become the critical bottleneck in many applications, and the speed-density trade-off between SRAM and DRAM poses a significant quandary faced by chip and system architects.; In this work, a novel negative differential resistance (NDR) based SRAM cell (called T-RAM) is introduced. T-RAM addresses the memory bottleneck by providing DRAM-like densities at SRAM-like speeds. The area of a T-RAM cell is less than one tenth the area of a conventional SRAM cell and equal to the area of a DRAM cell. The speed of a T-RAM cell is comparable to state-of-the-art SRAMs. Furthermore, the fabrication process for T-RAM is fundamentally compatible with mainstream CMOS.; A T-RAM cell is based on a thin capacitively coupled thyristor (TCCT) structure that uses a novel gate-assisted switching mechanism. In this thesis, the basic concept and the characteristics (both DC and transient) of a TCCT device are discussed. The fabrication of experimental prototypes of TCCT devices with planar NMOSFETs (the two components of T-RAM cells) are also presented. Our experimental results for T-RAM cells show a record-low standby current among NDR-based SRAMs that is less than 10pA/cell and a switching speed of about 5ns. The proposed Read/Write operations of a T-RAM cell and its gate-assisted switching mechanism are experimentally verified. The thermal stability of a T-RAM cell is also discussed via device simulations and experimental measurements. Compared to other types of NDR-based memories, T-RAM shows a much better thermal stability that can be further improved by sacrificing the cell standby current.
机译:在过去的二十年中,处理速度提高了三到四个数量级,而DRAM随机访问速度却提高了不到一个数量级。处理器和内存速度之间的巨大差距可以通过更快的技术来解决,例如SRAM,但是传统SRAM的使用受到了限制,因为它的密度比DRAM低一个数量级。处理器内存性能差距已成为许多应用程序中的关键瓶颈,而SRAM和DRAM之间的速度密度折衷成为芯片和系统架构师面临的巨大难题。在这项工作中,介绍了一种新颖的基于负差分电阻(NDR)的SRAM单元(称为T-RAM)。 T-RAM通过以类似SRAM的速度提供类似DRAM的密度来解决存储瓶颈。 T-RAM单元的面积小于传统SRAM单元的面积的十分之一,并且等于DRAM单元的面积。 T-RAM单元的速度可与最新的SRAM相提并论。此外,T-RAM的制造工艺与主流CMOS基本兼容。 T-RAM单元基于采用新型栅极辅助开关机制的薄电容耦合晶闸管(TCCT)结构。本文讨论了TCCT器件的基本概念和特性(直流和瞬态)。还介绍了带有平面NMOSFET(T-RAM单元的两个组件)的TCCT器件的实验原型的制造。我们对T-RAM单元的实验结果表明,基于NDR的SRAM中的待机电流低至10pA / cell,并且开关速度约为5ns。通过实验验证了提出的T-RAM单元的读/写操作及其栅极辅助开关机制。还通过器件仿真和实验测量来讨论T-RAM单元的热稳定性。与其他类型的基于NDR的存储器相比,T-RAM具有更好的热稳定性,可以通过牺牲单元待机电流来进一步提高其热稳定性。

著录项

  • 作者

    Nemati, Farid.;

  • 作者单位

    Stanford University.;

  • 授予单位 Stanford University.;
  • 学科 Engineering Electronics and Electrical.
  • 学位 Ph.D.
  • 年度 2001
  • 页码 166 p.
  • 总页数 166
  • 原文格式 PDF
  • 正文语种 eng
  • 中图分类 无线电电子学、电信技术;
  • 关键词

  • 入库时间 2022-08-17 11:47:09

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