Nanofabrication technologies and novel device structures for nanoscale CMOS.

摘要

This dissertation investigates new patterning technologies and novel device structures for sub-20nm complementary metal-oxide-semiconductor (CMOS). Ashing-trimming and spacer lithography technology for patterning sub-20nm features are investigated.; Ultra-thin body (UTB) metal-oxide-semiconductor field-effect transistors (MOSFETs) are demonstrated and they show excellent suppression of short-channel effects. One of its challenges is the large series resistance of the thin-body silicon. To overcome this difficulty, resist and poly-silicon etch-back process and selective germanium deposition are developed for raised source and drain. Devices with sub-30nm gate lengths, 750μA/μm of NMOS drive current, and 350μm/μm of PMOS drive current are demonstrated.; Thin body silicon can cause a change of sub-bands structure. As a result, threshold voltage shift and mobility enhancement are observed in UTB devices. Threshold voltage shift of UTB CMOS is modeled analytically and the model is verified with measured data. Mobility enhancement in the thin body is also examined.; Double-gate structure can provide more robustness against the short-channel effects. Simplified planar double-gate FinFETs are fabricated with two different patterning approaches: e-beam lithography and spacer lithography. Spacer lithography technology achieves twice the device density within a given pitch, which is limited by optical or e-beam lithography. It provides more uniform fin width, and ultimately narrower fins than what can be produced with conventional lithography. Devices with features below 60nm and drive current above 1000μA/μm (NMOS) and 760μA/μm (PMOS) have been demonstrated. Chemical-mechanical polishing (CMP) process is developed to overcome process challenges coming from the vertical device structures of FinFETs.; E-beam lithography with subsequent ashing-trimming has produced a 10nm silicon fin width and a sub-20mm gate length, which is the world record smallest transistor. Its NMOS drive current is 730μA/μm and PMOS drive current is 550μA/μm. Selective germanium is utilized to fabricate raised source and drain which minimize the parasitic series resistance and improve the drive current.