首页> 外文学位 >High dielectric constant gate oxides for III-V CMOS.
【24h】

High dielectric constant gate oxides for III-V CMOS.

机译:用于III-V CMOS的高介电常数栅极氧化物。

获取原文
获取原文并翻译 | 示例

摘要

III-V compound semiconductors are of interest as channel materials for next-generation metal-oxide-semiconductor field effect transistors (MOSFETs), as silicon devices reach their fundamental materials limitations. The high electron mobilities of III-V semiconductors potentially allow for higher saturation velocities and further performance scaling. High dielectric constant ( k) gate oxides are essential for MOSFET devices and are a major challenge in developing III-V MOSFETs. Interfaces between dielectrics and III-V semiconductors exhibit extremely large interface trap densities, which degrade the transistor performance. Quantitative methods are required to estimate the interface electrical properties and to optimize the interfaces. Methods developed for Si interfaces cannot directly be applied because of differences in the band structures.;In this dissertation, high-k gate dielectric deposition and quantitative interface analysis are developed, focusing on MOS capacitors (MOSCAPs) with In0.53Ga0.47As channels. By employing a ultra-high vacuum chemical beam deposition technique using alkoxide precursors, TiO2, ZrO2, and HfO2 gate dielectrics are developed. Their potentials and limitations as gate dielectrics for In 0.53Ga0.47As MOSFET are discussed. It is shown that growth modes and electrical properties are significantly improved by introducing an alkyl precursor (trimethylaluminium). MOSCAPs showing a 1 nm equivalent oxide thickness (EOT) and a relatively low interface trap density of 10 12 eV-1cm -2 are demonstrated with HfO2 dielectrics. Capacitance-based and conductance-based methods are developed for characterizing the interface trap density of In0.53 Ga0.47As MOSCAPs and guidelines are introduced to assess the electrical quality of high-k gate oxide/III-V interface.
机译:随着硅器件达到其基本材料极限,III-V族化合物半导体作为下一代金属氧化物半导体场效应晶体管(MOSFET)的沟道材料受到关注。 III-V半导体的高电子迁移率可能允许更高的饱和速度和进一步的性能定标。高介电常数(k)栅极氧化物对于MOSFET器件至关重要,并且是开发III-V MOSFET的主要挑战。电介质和III-V半导体之间的界面表现出极大的界面陷阱密度,这会降低晶体管的性能。需要使用定量方法来估计界面电性能并优化界面。由于能带结构的不同,无法直接应用为Si界面开发的方法。;本文针对具有In0.53Ga0.47As沟道的MOS电容器(MOSCAP),开发了高k栅极电介质沉积和定量界面分析。通过采用使用醇盐前体的超高真空化学束沉积技术,开发了TiO2,ZrO2和HfO2栅极电介质。讨论了它们作为In 0.53Ga0.47As MOSFET的栅极电介质的潜力和局限性。结果表明,通过引入烷基前体(三甲基铝)可以显着改善生长方式和电性能。使用HfO2电介质证明了具有1 nm等效氧化物厚度(EOT)和相对较低的界面陷阱密度为10 12 eV-1cm -2的MOSCAP。开发了基于电容和基于电导的方法来表征In0.53 Ga0.47As MOSCAP的界面陷阱密度,并引入了指南来评估高k栅极氧化物/ III-V界面的电气质量。

著录项

  • 作者

    Hwang, Yoontae.;

  • 作者单位

    University of California, Santa Barbara.;

  • 授予单位 University of California, Santa Barbara.;
  • 学科 Engineering Electronics and Electrical.;Engineering Materials Science.
  • 学位 Ph.D.
  • 年度 2011
  • 页码 182 p.
  • 总页数 182
  • 原文格式 PDF
  • 正文语种 eng
  • 中图分类
  • 关键词

相似文献

  • 外文文献
  • 中文文献
  • 专利
获取原文

客服邮箱:kefu@zhangqiaokeyan.com

京公网安备:11010802029741号 ICP备案号:京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有
  • 客服微信

  • 服务号