Reduced scaling of feature sizes and process variations in CMOS nano-technologies introduce manufacturing anomalies that reduce yield, and this trend is predicted to get worse for emerging technologies. In addition, it takes more time to be resolved these issues compared to previous technologies. Therefore, it will be increasingly more crucial to develop design techniques to enhance yield in emerging technologies. While logic circuits, namely gates and flip-flops, occupy a small amount of chip area, they are more critical compared to memories as their irregular structure makes it difficult to improve their yield. In addition, logic circuitry contains many single points of failure, and thus any killer defect in this circuitry can turn a die to scrap. This fact suggests the need to develop a highly efficient architectural design methodology based on using redundancy for logic circuits.;In this dissertation we use redundancy in logic circuits to improve silicon yield/area (a.k.a revenue per wafer). While most of the traditional techniques use redundancy at the core level; we show that for emerging technologies with low yield, redundancy needs to be used at lower level of granularity compared to core level (inter-level) to enhance yield and reduce time to market. Our theoretical and experimental results show a significant increase in yield and yield/area compared to the original circuit without redundancy.;To employ redundancy at fine level of granularity, we need to take into consideration the following issues: (i) design of steering logic - the generic term for a fork, join and switch - for logically selecting a redundant copy of a module to use as well as directing data to and from such modules, (ii) designing a support architecture for testing both the steering logic as well as the modules, (iii) estimating the overheads of steering logic such as their yield, area and delay, ( iv) finding appropriate number of spares for heterogeneous modules with different sizes (areas) and yields while taking into consideration the overheads of inserting testable and configurable steering logic, and ( v) partitioning the original circuit to find the optimal level of granularity for yield/area maximization using redundancy.;The focus of this dissertation is to develop CAD tool, algorithms, heuristics and theorems to address all these issues. We develop a layout-driven CAD tool (TYSEL) to precisely estimate the overheads of steering logic. Then we develop different algorithms and heuristics for yield and yield/area maximization of logic circuits with linear and non-linear structures. Our techniques take into account the overheads of steering logic (estimated by TYSEL) in their computations.;Finally, we introduce a theory of partitioning of the original logic circuit to capture the impact of granularity, and uniformity of partitions on yield/area after using redundancy. Based on our theoretical results, we present a design flow to find the optimal level of granularity for the given logic circuit to be used for redundancy. Our design flow satisfies the realistic issues of using redundancy at finer granularity, such as performance loss and DFT (design for testability).
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