With the increasing demand for more durable products, the necessity of designing more resilient products is evident. When it comes to electronic systems, many strategies have been applied to enhance the durability and performance of the operating circuits. For a long time, the main focus was to develop increasingly reliable components, however, yield enhancement techniques may not be sufficient for future technologies. As a solution to this, redundancy strategies are being introduced in order to regain reliability of circuits even if the individual components are not as reliable as desired. The use of logic redundancy and series or parallel association of transistors is proposed as a strategy in the design of fault tolerant logic gates (that are the basic elements of many complex computing structures), such as NAND and NOR. Fault injection simulations show that the reliability of these gates in the presence of random stuck-at faults may be increased by our design approach and that the strategy is extensible to more elaborate circuits.
展开▼
