Three-dimensional interconnects for die and wafer stacks

摘要

3D integration results from the ever demanding trend towards smaller, lighter and lower cost packaged devices. With the present System-on-chip (SOC) technology reaching its limitation in terms of functionality and cost, efforts are being concentrated on exploring the third dimension, i.e. 3D integration that provides a volumetric packaging solution for higher integration and performance. It can be achieved through die stacking and wafer stacking. A key technology to realize the potential of stacking is implementation of vertical electrical interconnects between die and wafer stacks.;This thesis discusses the approach to form vertical interconnects between wafer stacks through solder reflow and wafer level bonding. The processing recipe to achieve wafer bonding using photosensitive Benzocyclobutene (BCB) is developed. The fabrication process for formation of electrical interconnects through solder metal reflow is elaborated and surface profiles of the reflowed solder metal are included. This thesis also discusses die level bonding for hermetic packaging of a MEMS device. Vertical electrical interconnections between dies are formed through thermo-compression bonding. A process is developed to achieve die bonding through a fluxless soldering technique. Experiments were conducted using two different solder compositions bonding results with each are discussed.;Furthermore, low frequency and high frequency analysis of interconnects is performed. This analysis is used as guidelines to select the correct dimension for interconnects specific to the application.