This paper investigates the viability and compares the merits of small-signal differential sensing and large-signal single-ended sensing scheme for FinFET SRAM under fin Line-Edge-Roughness (fin LER) and Work-Function-Variation (WFV). The local random variation of selected cell, leakage (and its variation) from unselected cells on the selected Bit-Line (BL), and variation of sense amplifier offset voltage (for differential sensing) and trip voltage (for large-signal sensing) are considered simultaneously at subthreshold (Vdd=0.4V) and superthreshold (Vdd=1.0V) regions. For differential sensing, the subthreshold sensing margin is severely degraded by the variation in Bitline voltage and sufficient time before enabling the sense amplifier is required to improve the limited margin. For large-signal sensing scheme, we show that there is large disparity between the sense “0” margin and sense “1” margin with the significantly worse sense “0” margin limiting the affordable number of cells per Bitline. The possibility of using double-fin PFET in large-signal sensing inverter to improve the sense “0” margin is examined, and shown to be of limited benefit, especially for operation in subthreshold region. Compared with BULK CMOS, the superior electrostatic integrity and variability of FinFET enhances/enables the feasibility of differential sensing in subthreshold/superthreshold SRAM applications.
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