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A Temperature-Aware Placement and Routing Algorithm Targeting 3D FPGAs

机译:针对3D FPGA的温度感知布局和路由算法

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In current reconfigurable architectures, the interconnect structures increasingly contribute to the delay and power consumption budget. The demand for increased clock frequencies and logic availability (smaller area foot print) makes the problem even more important, leading among others to rapid elevation in power density. Three-dimensional (3D) architectures are able to alleviate this problem by accommodating a number of functional layers, each of which might be fabricated in different technology. Since power consumption is a critical challenge for implementing applications onto reconfigurable hardware, a novel temperature-aware placement and routing (P&R) algorithm targeting 3D FPGAs, is introduced. The proposed algorithm achieves to redistribute the switched capacitance over identical hardware resources in a rather "balanced" profile, reducing among others the number of hotspot regions, the maximal values of power sources at hotspots, as well as the percentage of device area that consumes high power. For evaluation purposes, the proposed approach is realized as a new CAD tool, named 3DPRO (3D-Placement-and-Routing-Optimization), which is part of the complete framework, named 3D MEANDER. Comparing to alternative solutions, the proposed one reduces the percentage of silicon area that operates under high power by 63%, while it leads to energy savings (about 9%), with an almost negligible penalty in application's delay ranging from 1% up to 5%.
机译:在当前的可重配置体系结构中,互连结构越来越多地影响延迟和功耗预算。对增加时钟频率和逻辑可用性(较小的占地面积)的需求使这个问题变得更加重要,从而导致功率密度的快速提高。三维(3D)架构能够通过容纳多个功能层来缓解此问题,每个功能层都可以用不同的技术制造。由于功耗是将应用程序实现到可重配置硬件上的关键挑战,因此引入了针对3D FPGA的新型温度感知布局和路由(P&R)算法。所提出的算法实现了在相当“平衡”的配置文件中在相同的硬件资源上重新分配开关电容,从而减少了热点区域的数量,热点处的电源最大值以及消耗高功率的设备面积的百分比。功率。出于评估目的,建议的方法是作为名为3DPRO(3D放置和路由优化)的新CAD工具实现的,该工具是名为3D MEANDER的完整框架的一部分。与替代解决方案相比,拟议中的解决方案将在高功率下工作的硅面积百分比降低了63%,同时节省了能源(约9%),应用延迟从1%到5几乎可以忽略不计%。

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