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Selective-capacitance constant-charge-injection programming scheme for high-speed multilevel AG-AND flash memories

机译：高速多级AG-AND闪存的选择电容恒电荷注入编程方案

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The market for flash memories has emphasized bit-cost reduction and high programming throughput because of demanding applications such as high quality digital still cameras and portable video recorders. One of the solutions to achieve low cost-per-bit is

机译：由于诸如高质量数码相机和便携式录像机之类的要求苛刻的应用，闪存市场一直强调降低位成本和提高编程吞吐量。实现低单位成本的解决方案之一是

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来源
《VLSI Circuits, 2005 IEEE Symposium on》|2005年|P.168-169|共2页
会议地点 KyotoJapan
作者
Otsuga; K.; Kurata; H.; Kozakai; K.; Noda; S.; Sasago; Y.; Arigane; T.; Kawamura; T.; Kobayashi; T.;
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charge-coupled devices; flash memories; 10 Mbit/s; 4 Gbit; CCIP; assist-gate-AND flash memories; cost-per-bit; digital still camera; memory cell threshold voltage; multilevel AG-AND flash memory; multilevel cell technique; portable video recorder; program verify ope;

机译：电荷耦合器件闪存； 10 Mbit / s； 4 Gbit； CCIP；辅助门与闪存；每位成本；数码相机存储单元阈值电压；多级AG-AND闪存；多级细胞技术便携式录像机；程序验证操作;

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专利

1. A Design of Constant-Charge-Injection Programming Scheme for AG-AND Flash Memories Using Array-Level Analytical Model [J] . Shinya KAJIYAMA, Kenichiro SONODA, Kazuo OTSUGA, IEICE Transactions on Electronics . 2008,第4期

机译：基于阵列级分析模型的AG-AND快闪存储器恒充注入编程方案设计
2. Constant-Charge-Injection Programming: A Novel High-Speed Programming Method for Multilevel Flash Memories [J] . Hideaki Kurata, Shunichi Saeki, Takashi Kobayashi, IEEE Journal of Solid-State Circuits . 2005,第2期

机译：恒定电荷注入编程：一种用于多层闪存的新型高速编程方法
3. High-Speed Multilevel nand Flash Memory With Tight $V_{rm th}$ Distribution Using an Engineered Potential Well and Forward-Bias Adjusted Programming [J] . Zhang G., Wu Z., Yoo W. J. Electron Devices, IEEE Transactions on . 2011,第10期

机译：采用工程势阱和正向偏置调整编程，紧密分配$ V_ {rm th} $的高速多级nand闪存
4. Selective-capacitance constant-charge-injection programming scheme for high-speed multilevel AG-AND flash memories [C] . Otsuga, K., Kurata, . 2005

机译：高速多级AG-AND闪存的选择电容恒电荷注入编程方案
5. Rewriting Schemes for Flash Memory. [D] . En Gad, Eyal. 2015

机译：闪存的重写方案。
6. Novel Program Scheme of Vertical NAND Flash Memory for Reduction of Z-Interference [O] . Su-in Yi, Jungsik Kim 2021

机译：用于减少Z干扰的垂直NAND闪存的新型程序方案
7. Adaptive Pulse Programming Scheme for Improving the Vth Distribution and Program Performance in 3D NAND Flash Memory [O] . Zhichao Du, Shuang Li, Yu Wang, 2021

机译：自适应脉冲编程方案，用于提高3D NAND闪存中的Vth分布和节目性能

Selective-capacitance constant-charge-injection programming scheme for high-speed multilevel AG-AND flash memories

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