A 0.18 μm CMOS TECHNOLOGY FOR ELEVATED SOURCE /DRAIN MOSFETs USING SELECTIVE SILICON EPITAXY

摘要

A 0.18 μm technology for Elevated Source /Drain (ESD) devices is described in this paper. Key processes that must either be incorporated or modified due to the integration of the elevated layer into a conventional MOSFET structure are discussed. Included in this list are the deposition and doping of a selectively grown epitaxial Si layer, surface preparation prior to the deposition, choice of isolation strategy and sidewall spacer formation. Epitaxial growth in fabricated devices was carried out with high selectivity and low thermal budgets. Adequate confinement of the Si epi in active areas was achieved using LOCOS isolation, though some lateral overgrowth was observed in depositions at higher pressures. ESD MOSFETs with L_(eff) down to 0.15 μm are reported. An improved drive current due to reduced series resistance is confirmed for the ESD structure over conventional non-elevated LDD structures.