ELECTROLESS DEPOSITION AS ENABLING TECHNOLOGY FOR SEMICONDUCTOR PROCESSING

摘要

The continuous shrink of IC interconnect is approaching the moment of a transition from bulk polycrystalline metals to material properties of sub-unit cell films introducing new process integrations challenges and making reliability requirements one of the most important parameters in semiconductor industry. The new Ultra LOW-k materials may fail to provide a practical and inexpensive solution for high volume manufacturing thus leaving metal interconnect and associated integration solutions as the most effective path to higher IC performance. The problem of integration of relatively high-k dielectric diffusion barriers such as SiN(O,C) between copper layers with poor adhesion to the said dielectric barriers warranty the introduction of selective conductive barriers, which could be deposited through electroless deposition (ELD) process selectively as cap layers on Cu after CMP. We review the advantages and difficulties of selective ELD deposition processes integration as well as new device manufacturing technologies such as air gap, promising a significant IC manufacturing cost reduction and expansion of IC market without increase of capital costs building new fabs. The most recent examples of our research on ELD deposition and integration are presented, including metrology, yield, and chemical formulations review.