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A Modular Simulator Framework for Network-on-Chip Based Manycore Chips Using UNISIM

机译:使用UNISIM的基于芯片网络的Manycore芯片的模块化仿真器框架

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NoC-based manycore chips are considered as emerging platforms of significant importance but so far there is no public accessible architectural sim ulator which allows coupled simulation of NoC and cores for relevant research. This paper presents a modular cycle-level simulator framework developed using UNISIM and its applicability is exemplified by building a simulator which mod els a message-passing distributed memory architecture with an NoC and supports coupled simulation. Simulation of a MPI-based parallel program on this simu lator shows that performance metrics, such as throughput, delay and overhead, can be accurately evaluated with the captured data of flits and messages. Simu lators for different functionalities and architectures can be constructed by using this framework.
机译:基于NoC的manycore芯片被认为是非常重要的新兴平台,但到目前为止,还没有公共可访问的体系结构模拟器允许对NoC和内核进行耦合仿真以进行相关研究。本文介绍了使用UNISIM开发的模块化周期级仿真器框架,其适用性通过构建一个仿真器来举例说明,该仿真器使用NoC对消息传递的分布式内存架构进行建模,并支持耦合仿真。在此仿真器上对基于MPI的并行程序进行的仿真显示,可以使用捕获的碎片和消息数据准确评估性能指标,例如吞吐量,延迟和开销。使用此框架可以构建用于不同功能和体系结构的仿真器。

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