A Modular Simulator Framework for Network-on-Chip Based Manycore Chips Using UNISIM

摘要

NoC-based manycore chips are considered as emerging platforms of significant importance but so far there is no public accessible architectural sim ulator which allows coupled simulation of NoC and cores for relevant research. This paper presents a modular cycle-level simulator framework developed using UNISIM and its applicability is exemplified by building a simulator which mod els a message-passing distributed memory architecture with an NoC and supports coupled simulation. Simulation of a MPI-based parallel program on this simu lator shows that performance metrics, such as throughput, delay and overhead, can be accurately evaluated with the captured data of flits and messages. Simu lators for different functionalities and architectures can be constructed by using this framework.