A Crossing Charge Recycle Refresh Scheme with a Separated Driver Sense-Amplifier for Gb DRAMs

摘要

A crossing charge recycle refresh (CCRR) scheme is proposed for large capacity DRAMs with hierarchical bit-line architecture, which reduces main bit-line charging current to 25% of that of conventional DRAMs. A separated driver sense-amplifier (SDSA) circuit is essential to realize this scheme because it features 11 times shorter charge transfer period than that of conventional sense-amplifiers. These circuits are applied to an experimental 1-Gb DRAM.