SHALLOW JUNCTIONS FOR SUB-100 NM CMOS TECHNOLOGY

摘要

This paper studies the use of ion implantation and rapid thermal annealing for the fabrication of shallow junctions in sub-100 nm CMOS technology. Spike annealing recipes were optimized on the basis of delta-doping diffusion experiments and shallow junction characteristics. In addition, using GeF_2 pre-amorphization implants in combination with low-energy BF_2 and spike annealing, p-type junctions depths of 30 nm were obtained with sheet resistances as low as 390 Ω/sq. The combined finettuning of implantation and annealing conditions is expected to enable junction scaling into the 70-nm CMOS technology node.