Polycide Gate Etching and Oxide Charging Damage Evaluation in the Quarter-Micron DRAM Process

摘要

We report a study of polycide gate etching and oxide charging damage evaluation in the quarter-micron dynamic random access memory(DRAM) process. Gate etching processes using electron cyclotron resonance(ECR) plasmas or inductively coupled plasma(ICP) sources of two commercial polycide etch systems for 8-inch-#PHI# wafers are optimized with respect to parameters including SiN hard-mask selectivity, etched gate profile, etching critical dimension(CD) bias, and post-etching gate-oxide remaining thickness. Gate-oxide charging damage is characterized with time-to-breakdown(T_(bd)), charge-to-breakdown(Q_(bd)), and initial-electron-trapping-rate(IETR, dV/dt) measurements using metal-oxide-semiconductor(MOS) capacitors. Wafer charging in polycide gate over-etching stages is characterized with maps of wafer surface potential and J-V(current density versus voltage) plots using commercial CHARM~circleR-2 monitors. Correlation, sensitivity and limitations of these measurement methods are demonstrated in evaluating charging-up characteristics of these gate etching processes.