Energy Efficient Interface Circuits between Adiabatic and Standard CMOS logic at 90 nm Technology

摘要

Adiabatic circuits and standard CMOS logic are widely employed in Low power VLSI chips to achieve high system performance. The power saving of adiabatic circuit can reach more than 90% compared to conventional static CMOS logic. The clocking schemes and signal waveforms of adiabatic circuits are different from those of standard CMOS circuits. This paper investigates the design approaches of low-power interface circuits in terms of energy dissipation. Several low-power interface circuits that convert signals between adiabatic logic and standard CMOS circuits are presented. With BSIM 3v3 90 nm CMOS technology, the energy consumption of proposed interface circuits has relatively large power saving over the wide range of frequencies. This paper also investigates the different power delay product over the wide range of supply voltages. Simulation has been done on tanner EDA tool at BSIM 3v3 90nm technology.