Integration of High Aspect Ratio Structures

摘要

The nanometer regime challenges the vertical dimension of the nanoscale device structures due to many scaling constraints. For instance, device performance requirements, such as low line resistance, requisite barrier performance, high capacitance for DRAM capacitors, low capacitance between interconnect layers, and deep trenches for isolation, limit vertical scaling. Moreover, process integration considerations, including etch selectivity during dry etch, polish stop margin for CMP, and defect considerations, limit the thickness of films and material stacks during the fabrication of IC chips. The high aspect ratio nanostructures complicate the process integration of the device components, as well as the mechanical stability during and after fabrication.