A systematic approach for extracting verification patterns from an OPC test mask

摘要

Optical Proximity Correction (OPC) is a crucial step in Semiconductor manufacturing for technology of dimensionsbelow the exposure wavelength. Light from the exposure source is diffracted when passing through mask dimensionsbelow the exposure wavelength causing patterns on wafer to differ from the intent patterns. During OPC the designintent layout patterns are modified to compensate for light diffractions so that the final wafer patterns match the designintent patterns. OPC achieves this by using OPC models that model the optical conditions, resist, and etch behavior; andan OPC recipe that controls the patterns modification process. The OPC models are calibrated from test mask structuresthat are developed, exposed and measured when starting to set up the manufacturing process.Structures chosen to be placed on the test mask have a great impact on the capability to predict future layout patterns thatwere not present in the original test mask, referred to as model coverage. Test masks are usually composed of patternsused in model calibration and others used for verifying the calibrated model. In advanced technology nodes, both thefeature size and the error budget are being shrunk. Hence to reach the best model coverage with acceptable accuracy, weneed to ensure that the test mask contains all the possible structures in the real designs, while maintaining that thenumber of patterns does not consume long metrology tools time, cause extra overhead cost to the process, or delay thedevelopment cycle.This paper presents a systematic approach to optimize the number of patterns to be included in the test mask and splittest patterns into calibration and verification patterns. Results from using the proposed method are compared to othermethods of splitting that are based either on geometrical or random methods. The approach provided a significantreduction in model calibration time, the number of needed patterns in the test mask, and the total development processturn-around time; while maintaining the same accuracy that can be achieved from the original test patterns set.© (2012) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.