Chip-level Performance Maximization using ASIS (Application-specific Interconnect Structure) Wiring Design Concept for 45 nm CMOS Devices

摘要

A novel interconnect design concept named "ASIS (Application-specific Interconnect Structure)" is presented for 45 nm CMOS performance maximization. Basic scheme of ASIS is that corresponding to applications, such as high-performance, low-power or high reliability, interconnect structure as well as metal thickness is individually optimized in order to maximize chip-level performance matched to the application. Our investigation shows that for low power application, the increased resistivity of scaled-down Cu-wire is not a main issue, so that thinner wire is more advantageous. For high-performance application, partially double pitch structure for local and intermediate layers is advantageous. For high-reliability requirement, CuAl-alloy or CoWP cap-metal is quite effective for boosting reliability.