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1700V/30A 4H-SiC MOSFET with low cut-in voltage embedded diode and room temperature boron implanted termination

机译:1700V / 30A 4H-SIC MOSFET具有低切割电压嵌入式二极管和室温硼植入终止

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In this paper, a SiC MOSFET embedded with a low cut-in voltage Schottky diode was proposed. The 1V cut-in voltage of embedded Schottky diode, which is lower than the 3V cut-in voltage of parasitic body diode, can prevent the potential failures caused by the transformation of dislocation defects into stacking faults due to the recombination of injected minority carriers when parasitic body diode in SiC MOSFET was turned on. The voltage drop of forward biased embedded diode at a current density of 75 A/cm is 1.7V, compared to the 4.9V in the parasitic body diode, is helpful to reduce the energy loss. The terminations with floating guard rings formed by aluminum implantations at 500°C and an extended coupling band formed by boron implantations at room temperatures were able to achieve a blocking voltage of up to 1889V with a drift layer of 11μm thickness and 6×10 cm doping concentration. This termination provided a very tight distribution of blocking voltages with an average value of 1797V and a sigma of 43V or a mean to sigma value of only 2.4%, for 28 devices across the wafer. The working of the extended coupling band formed by room temperature implantation is speculated different from the ordinary junction termination extension (JTE) as the single zone JTEs formed by the room temperature boron implantations could provide blocking voltages of about 500V, which is essentially of the same level for devices without terminations. A highly resistive region formed due to unrecoverable damages caused by room temperature implantations was considered to provide stable coupling between guard rings and thus improve the blocking voltage.
机译:在本文中,提出了一种嵌入具有低切换电压肖特基二极管的SiC MOSFET。嵌入式肖特基二极管的1V切口电压,低于寄生体二极管的3V切口电压,可以防止由于注入的少数载体的重组而导致脱位缺陷的转化变成堆叠故障引起的潜在故障SiC MOSFET中的寄生体二极管接通。与寄生体二极管中的4.9V相比,电流密度为1.7V的正向偏置二极管的电压降,有助于降低能量损失。具有在500℃下由铝植入形成的浮动环的终端和在室温下由硼注入形成的扩展耦合带,能够实现高达1889V的阻塞电压,漂移层厚度为11μm厚度,6×10cm掺杂专注。该终端提供了平均值为1797V的阻塞电压和43V的Sigma的平均值的非常紧密的分布,或者σ值仅为2.4%,对于晶片的28个器件仅为2.4%。由室温植入形成的扩展耦合带的工作被推测不同于普通的结终端延伸(JTE),因为室温硼注入形成的单个区域JTE可以提供约500V的阻塞电压,这基本上是相同的没有终结的设备级别。由于室温注入引起的不可恢复损坏而形成的高电阻区域被认为是在保护环之间提供稳定的耦合,从而提高阻挡电压。

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