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1700V/30A 4H-SiC MOSFET with low cut-in voltage embedded diode and room temperature boron implanted termination

机译:1700V / 30A 4H-SiC MOSFET,具有低切入电压嵌入式二极管和室温硼注入终端

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In this paper, a SiC MOSFET embedded with a low cut-in voltage Schottky diode was proposed. The 1V cut-in voltage of embedded Schottky diode, which is lower than the 3V cut-in voltage of parasitic body diode, can prevent the potential failures caused by the transformation of dislocation defects into stacking faults due to the recombination of injected minority carriers when parasitic body diode in SiC MOSFET was turned on. The voltage drop of forward biased embedded diode at a current density of 75 A/cm is 1.7V, compared to the 4.9V in the parasitic body diode, is helpful to reduce the energy loss. The terminations with floating guard rings formed by aluminum implantations at 500°C and an extended coupling band formed by boron implantations at room temperatures were able to achieve a blocking voltage of up to 1889V with a drift layer of 11μm thickness and 6×10 cm doping concentration. This termination provided a very tight distribution of blocking voltages with an average value of 1797V and a sigma of 43V or a mean to sigma value of only 2.4%, for 28 devices across the wafer. The working of the extended coupling band formed by room temperature implantation is speculated different from the ordinary junction termination extension (JTE) as the single zone JTEs formed by the room temperature boron implantations could provide blocking voltages of about 500V, which is essentially of the same level for devices without terminations. A highly resistive region formed due to unrecoverable damages caused by room temperature implantations was considered to provide stable coupling between guard rings and thus improve the blocking voltage.
机译:本文提出了一种嵌入了低切入电压肖特基二极管的SiC MOSFET。嵌入式肖特基二极管的1V切入电压低于寄生体二极管的3V切入电压,可以防止由于注入的少数载流子的重组而将位错缺陷转化为堆叠缺陷而引起的潜在故障。 SiC MOSFET中的寄生二极管已打开。与寄生体二极管中的4.9V相比,电流密度为75 A / cm时的正向偏置嵌入式二极管的压降为1.7V,这有助于降低能量损耗。在500°C的温度下通过铝注入形成的带有浮动保护环的终端以及在室温下通过硼注入形成的扩展耦合带,能够在厚度为11μm的漂移层和6×10 cm的掺杂下实现高达1889V的阻断电压浓度。对于整个晶片上的28个器件,此端接提供了非常紧密的阻断电压分布,其平均电压为1797V,西格玛值为43V,或均值至西格玛值仅为2.4%。据推测,由室温注入形成的扩展耦合带的工作方式不同于普通结终止扩展(JTE),因为由室温硼注入形成的单区JTE可以提供约500V的阻断电压,这基本上是相同的没有终端的设备的电平。人们认为,由于室温注入引起的不可恢复的损坏而形成的高电阻区域可在保护环之间提供稳定的耦合,从而提高阻断电压。

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