The technological limits of the channel length junction depth and oxide thickness for silicon devices are estimated to be 0.1/splmu/m, 005/spl mu/m, and 40/spl Aring/, respectively. The implication of these design rules for the ESD sensitivity of IC devices is investigated by using models of thermal breakdown and dielectric breakdown. A factor of 10 shrinkage in feature sizes makes pn junctions 5 times and gate oxides 10 times more sensitive to electrical stresses such as ESD.
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