Adjustment of the BEOL for back side module integration on wafer level in a silicon photonic technology

摘要

In this work, we investigated process adjustments of the passivation module of a full back end of line (BEOL) in order to realize a backside module integration on wafer level on silicon on insulator (SOI) substrate. We performed local backside release processes of photonic components with different passivation iterations and analysed possible impacts on the wafer surface using scattering electron microscopy. This work enables new approaches for a back side module integration on wafer level in SOI based electronic photonic integrated circuits (ePIC) technology platforms.