PHYSICAL DESIGN FOR AN ARM CHIP UNDER DEEP SUBMICRON TECHNOLOGY

摘要

The reduction of technology size presents lots of new challenges to the physical design of VLSI chips, such as timing closure, routability, signal integrity, IR drop and antenna effect. This paper introduces the physical design flow of an ARM processor chip, specifically describes some of the key steps, such as floorplan, clock tree synthesis, design for manufacturability, and it can provide a reference for other similar designs. The chip using SMIC 130nm process includes ADC, PLL and a plurality of SRAM. The master clock frequency is 200M and the chip area is 4mm * 5mm.