System-on-chip (SoC) design methodology and implementations for neural implants using deep submicron CMOS.

摘要

Rapid advancement in CMOS fabrication technology enables a wide-range of new smaller, lower power usage, better and faster electronic devices appear on the market. Yet, the biomedical devices or more specifically neurophysiology/electrophysiology research systems for neural recording and stimulation are not miniaturized and intergrated. On the same note, the commercial available neural stimulators such as the one for deep brain stimulation, have very limited functional features and not yet reduced in size despite of the recent improvement in electronics. The lack of a small implantable or carriable by a small rodent system leads to the development of a neurotechnology research system that can record and process neural signals and generate stimulation, which all are shrunk to a system-on-a-chip (SoC) packaged into a multi-chip module (MCM).;This thesis presents a design methodology and implementation examples a neurotechnology research system on a SoC that can be extended in functionalities with the additional specialized chips. A close-up examination of an end-to-end neural recording system, enables doing system design trade-off, begins with the fundamental study on the neuron. It is shown that the neurons themselves contribute the greatest noise, neural noise, in a neural recording. To overcome this problem, new adaptive and noise-shaping filtering techniques are employed in a neural signal processor. The neural signal processor of which is used to extract a spike from a continuous recording, grouping spike segments, filtering and extracting spike features. To make it a complete SoC, a rich full features open source CPU is integrated into the design providing a general purpose computing, such can be used for executing additional neural signal processing algorithms or spikes classification. The CPU is an OpenRISC from the OpenCores community that also comes with a full software toolchain support enables a rapid software development. A complete neural signal processor SoC, that has interconnection hooks readily to be integrated with a new 65nm multi-channel neural recording front-end, is implemented in 65nm with six metal layers CMOS process occupies an area of 685 x 670mum² with a power consumption of 11.2mW.;A complete neurotechnology research system in a MCM can not be achieved without a neural stimulator. This thesis also presents a design of an intelligence neural stimulator that comes with a stimulation monitoring system and a digital controller that provides lots of features and controllability of a device. It provides the flexibility of stimulating at any sites, at any time, in any random order with any type of stimuli patterns. This can be use to study the effects of stimulation propagation or virtual electrodes concepts. The design is fabricated in 0.35mum with four metal layers CMOS process occupies an area of 3.4 x 2.7mm² and consumes 2.3mW.