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Surface Preparation and In/Ga Alloying Effects on InGaAs(001)-(2×4) Surfaces For ALD Gate Oxide Deposition

机译:用于ALD栅极氧化物沉积的InGaAs(001) - (2×4)表面的表面制备和In / Ga合金作用

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High resolution STM images of In_(0.53)Ga_(0.47)As(001)-(2×4) were obtained and surface defects were quantified as a function of sample preparation technique. Published STM images of InGaAs(001)-(2×4) samples of varying In composition were examined and missing dimer unit cells, adatom trough defects, and incomplete atomic terraces were quantified for comparison with the In_(0.53)Ga_(0.47)As(001)-(2×4) surface. Density Functional Theory (DFT) modeling of α2(2×4) and β2(2×4) unit cell constructions and electronic structures show that the missing dimer defect creates conduction band edge states not readily passivated by trimethy aluminum; therefore, the density of dimer defects may cause trap state formation at oxide/InGaAs(001) interfaces.
机译:获得In_(0.53)Ga_(0.47)的高分辨率STM图像作为(001) - (2×4),用样品制备技术的函数量化表面缺陷。被出现的Ingaas(001) - (2×4)在组合物中的样品(2×4)样品被检查,并缺少二聚体单元电池,缺少的二聚体缺损和不完全的原子露台以与IN_(0.53)GA_(0.47)相比进行比较(001) - (2×4)表面。 α2(2×4)和β2(2×4)单元电池结构和电子结构的密度函数理论(DFT)建模表明,缺失的二聚体缺陷产生了不容易通过三甲基铝钝化的导带边缘状态;因此,二聚体缺陷的密度可以在氧化物/ ingAAs(001)界面处引起陷阱状态形成。

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