This paper presents a novel method to improve the performance of sub-threshold (sub-VT) gates in 65-nm CMOS technology. Faster transistors with a lower threshold voltage are introduced in the weaker network of a gate. It is shown that the employed method significantly enhances the reliability and performance of the gate, with an additive advantage of a lower area cost compared to traditional transistor sizing. Extensive Monte-Carlo simulations are carried out to verify the proposed optimization technique. The simulation results predict that the NAND3 and NOR3 testbench shows a 98% higher noise margin. Furthermore, the inverter and NAND3 gates show an speed improvement of 48% and 97%, respectively.
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机译：本文提出了一种新的方法，可以提高65-NM CMOS技术中的子阈值（Sub-V T ）栅极的性能。在栅极的较弱网络中引入具有较低阈值电压的更快晶体管。结果表明，与传统的晶体管施胶相比，采用的方法显着提高了栅极的可靠性和性能，其具有较低区域成本的添加剂优势。进行广泛的Monte-Carlo仿真，以验证所提出的优化技术。仿真结果预测NAND3和NOR3 TESTBENCH显示出98％的噪声裕度。此外，逆变器和NAND3栅极分别显示出48％和97％的速度提高。
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