This paper presents a novel method to improve the performance of sub-threshold (sub-VT) gates in 65-nm CMOS technology. Faster transistors with a lower threshold voltage are introduced in the weaker network of a gate. It is shown that the employed method significantly enhances the reliability and performance of the gate, with an additive advantage of a lower area cost compared to traditional transistor sizing. Extensive Monte-Carlo simulations are carried out to verify the proposed optimization technique. The simulation results predict that the NAND3 and NOR3 testbench shows a 98% higher noise margin. Furthermore, the inverter and NAND3 gates show an speed improvement of 48% and 97%, respectively.
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机译：本文提出了一种新的方法来提高65nm CMOS技术中的亚阈值（sub-V T ）门的性能。具有较低阈值电压的较快晶体管被引入到较弱的栅极网络中。结果表明，与传统晶体管尺寸相比，所采用的方法显着提高了栅极的可靠性和性能，并具有较低的面积成本的附加优势。进行了广泛的蒙特卡洛仿真，以验证所提出的优化技术。仿真结果预测，NAND3和NOR3测试台的噪声容限提高了98％。此外，反相器和NAND3门的速度分别提高了48％和97％。
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