Devices using fully depleted undoped channels are among the most promising candidates for the next device generations due to their better immunity to short channel effects (SCE) (1) and to random dopant fluctuation. Channel engineering and control are then critical as silicon thickness fluctuation is a statistical source of V_T variability and strained channels provide 47% increase in the drive current for NFETs (2) without any degradation for PFETs (3). SOI substrates from Soitec provide a complete set of manufacturing solutions either for planar or three-dimensional (FinFET) devices as they pre-integrate critical characteristics of the transistors within the wafer structure itself. Substrate robustness and readiness have been demonstrated. For planar devices the SOI thickness uniformity is controlled at +/-5A (6sigma value, all sites, all wafers) in high volume manufacturing mode. For three-dimensional devices, substrate requirements are extremely close to partially depleted ones which are in high volume manufacturing for more than 7 years.
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