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Angle-of-attack investigation of pin-fin arrays in nonuniform heat-removal cavities for interlayer cooled chip stacks

机译:间层间冷却芯片叠层非均匀散热空腔销翅片阵列的攻击性研究

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Interlayer cooling removes the heat dissipated by vertically stacked chips in multiple integrated fluid cavities. Its performance scales with the number of dies in the stack and is therefore superior to traditional back-side heat removal. Previous work indicated that pin-fin arrays are ideally suited as through-silicon-via-compatible heat transfer structures. In addition, four-port fluid-delivery and fluid-guiding structures improve the heat-removal performance for the nonuniform power maps of high-performance microprocessor chip stacks. Accordingly, an extension of the porous-media multi-scale modeling approach is presented as an efficient approach for designing nonuniform heat transfer cavities. A tensor description in combination with a look-up table is proposed to physically describe periodic porous media, such as pin-fin arrays, in detail. Conjugate heat and mass transfer sub-domain modeling is performed with periodic boundary conditions to derive the orientation-dependent permeability and angle offset between the pressure gradient and the Darcy velocity direction for pin-fin arrays with a pin diameter of 50 μm and pitch and height of 100 μm. A local permeability minimum at a flow direction of approx. 30° could be identified. At higher velocities, the fluid flow is biased towards the symmetry lines of the pin-fin array. The modeling concept was validated with experimental readings of a nonuniform, double-side-heated single test cavity. The main characteristics of the temperature field with respect to the four-port architecture, the guiding structures, the fluid temperature increase, and the nonuniform power dissipation are predicted correctly. A statistical comparison of power maps with different heat transfer contrast values resulted in a mean accuracy <6% at a maximal standard deviation of 22.2%. Finally, the potential of the four-port architecture for nonuniform power maps with hot spots in the corners was demonstrated.
机译:层间冷却去除通过在多个集成流体腔中的垂直堆叠芯片消散的散热。它的性能尺度与堆叠中的模具数量相比,因此优于传统的背面热量。以前的工作表明,PIN翅片阵列非常适合作为硅通孔兼容的传热结构。此外,四端口流体输送和流体引导结构提高了高性能微处理器芯片堆叠的非均匀功率图的散热性能。因此,介绍了多孔介质多尺度建模方法的延伸,作为设计非均匀传热腔的有效方法。提出了与查找表的组合的张解器描述,以详细地描述周期性多孔介质,例如销鳍阵列。缀合物热量和质量传递子域建模是通过周期性边界条件进行的,以导出压力梯度和达曲速度方向之间的取向依赖性渗透率和角度偏移,用于销鳍阵列,销钉直径为50μm,间距和高度100μm。局部渗透率最小在大约的流动方向上。可以识别30°。在较高的速度下,流体流朝向销鳍阵列的对称线偏置。使用非均匀双侧加热的单个测试腔的实验读数验证了建模概念。正确预测温度场相对于四端口架构,引导结构,流体温度升高和非均匀功耗的主要特征。具有不同传热对比度值的功率图的统计比较导致平均精度<6%在最大标准偏差为22.2%。最后,证明了拐角中具有热点的非均匀电源图的四端口架构的潜力。

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