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Metal Gate Effects on a 32 nm Metal Gate Resistor

机译:32nm金属栅极电阻上的金属栅极效应

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At the 32 nm technology node, the change from a P+ polysilicon / SiON gate stack to a P+ A-silicon/metal gate/high-K dielectric will have a significant impact on RF passives, especially the MOSCAPs and gate resistors. The low sheet resistance value of the metal gate resistor will cause its size to increase. As shown in Figs. 7, 8, and 9, the metal gate resistor TC ranges from positive values for resistors with longer length and narrower width to negative values for resistors with shorter length and wider width. This strong temperature performance dependence on L&W may limit the L&W ranges of analog metal gate resistor designs.
机译:在32nm技术节点中,从P +多晶硅/ SiON栅极堆叠到P + A-硅/金属栅极/高k电介质的变化将对RF无源具有显着影响,尤其是模型和栅极电阻。金属栅电阻器的低薄层电阻值将导致其尺寸增加。如图1和图2所示。如图7,8和9所示,金属栅极电阻器TC从具有较长长度更长的电阻器的电阻器的正值范围与具有较短长度和更宽宽度的电阻器的宽度较窄到负值。这种强烈的温度性能依赖于L&W可以限制模拟金属栅极电阻器设计的L&W范围。

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