3D chip stacking realize high density packaging and high speed performance. High aspect ratio through silicon via allow short interconnects and reduced signal delays. Copper has been selected as the through silicon via because of its compatibility with conventional multilayer interconnection in large scale integration (LSI) and back end processes. Copper electrodeposition in high aspect ratio via is one of the key technologies for 3D packaging. This electrodeposition occupies almost 40% of the total TSVcost(l). Voids or seams formed in the via may causes serious problems in reliability. RIE and TiN barrier layer formation and copper seed layer formation require about 10 minutes according to ASET(2). With high speed slurry, the CMP time can also be reduced to about 10 minutes. K.Takahashi(3) simulated the process cost of their 3D packaging. Copper electrodeposition require several hours(4,5) and would be the rate determining step, and so the reduction of the electrodeposition time is required. The objective of this study is to fill the via of aspect ratio of 7.0(10 μm in diameter and 70 u m in depth via) and reduce the electrodeposition time to 30minutes or less to make this step compatible with the other operations.
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