With the extensive research on through-silicon-via (TSV) and die-stacking technology from both academia and industry, mainstream production of 3D ICs is expected in a near future. However, power delivery is believed to be one of the most challenging problems in 3D ICs. A main objective of the 3D power/ground (P/G) network optimization is to minimize the usage of P/G TSVs while satisfying power supply noise constraint. P/G TSVs consume a considerable amount of routing resources unless designed carefully. In this work, we first investigate the impact of P/G TSVs on the power supply noise as well as 3D IC layouts. We perform sign-off static IR-drop analysis on GDSII layouts of 2D and 3D IC designs using commercial-grade tools. We also explore the impact of 3D P/G network topology on IR-drop by varying P/G TSV pitch. Next, we propose a non-regular P/G TSV placement algorithm to further reduce the number of P/G TSVs used while satisfying the given IR-drop noise requirement. Compared with the conventional regular structure, our non-regular P/G TSV placement algorithm reduces the P/G TSV count, wirelength, and footprint area by 59.3%, 3.4%, and 3.5% on average, respectively.
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机译：随着穿透硅通孔（TSV）和来自学术界和工业界芯片堆叠技术，生产主流3D IC的在不久的将来有望广泛的研究。然而，电力输送被认为是在3D IC的最具挑战性的问题之一。主要目的的3D电源/接地的（P / G）网络优化是同时满足电源噪声约束，以尽量减少P / G TSV的使用情况。 P / G的TSV消耗大量除非精心设计的路由资源。在这项工作中，我们首先探讨P / G TSV的对电源噪声以及3D IC布局的影响。我们进行签收的2D和3D IC的GDSII布局静态IR降分析设计使用商业级的工具。我们还通过改变P / G TSV音调探索IR压降3D P / G网络拓扑的影响。接着，我们提出了一种非规则P / G TSV放置算法，以进一步减少P的数目/ G的TSV同时满足给定的IR降噪声要求使用。与传统的规则的结构相比，我们的非正规P / G TSV放置算法分别59.3％，3.4％，平均为3.5％，减少了P / G TSV计数，线长，和接地区域。
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