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Reliability Issues for Nano-scale CMOS Dielectrics: - From Transistors to Product Reliability - From SiON to High-K dielectrics

机译:纳米规模CMOS电介质的可靠性问题: - 从晶体管到产品可靠性 - 从Sion到高k电介质

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Continuous scaling, necessary for enhanced performance and cost reduction, has pushed existing CMOS materials much closer to their intrinsic reliability limits, forcing reliability engineers to get a better understanding of circuit failure. This requires that designers will have to be very careful with phenomena such as high current densities or voltage overshoots. In addition to the reliability issues, new materials as metal gates and high-k gate dielectrics have been integrated. These new materials require that we gain understanding of the reliability physics related to these new materials and that we develop high confidence-level design rules. These new materials require a high understanding level of their reliability issues, as well as the development of high confidence level design rules.
机译:增强性能和成本降低所需的连续缩放推动了现有的CMOS材料更接近其内在的可靠性限制,强制可靠性工程师更好地了解电路故障。这要求设计人员必须非常小心,如高电流密度或电压过冲等现象。除了可靠性问题之外,还集成了新材料作为金属栅极和高k栅极电介质。这些新材料要求我们了解与这些新材料相关的可靠性物理,并开发出高信任级别的设计规则。这些新材料需要高度了解其可靠性问题,以及高置信水平设计规则的发展。

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