Non-Planar Devices for Nanoscale CMOS

摘要

In this paper, various concepts of multi-gate transistors are discussed with regards to their technological feasibility and manufacturability. In addition, non-standard fabrication process modules for triplegate nanoscale MOSFETs and sub-10 nm nanowires are presented. Alternatives to costly extreme ultraviolet (EUV) lithography are proposed as well as a self-aligned nickel silicide module to reduce inherent parasitic access resistances.