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Impact of Low-K Wire Bond Stacked Flip Chip CSP Package Material on Reliability Test

机译:低k线键堆叠芯片CSP封装材料对可靠性测试的影响

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As the consumer electronics market expending, system-in-package (SiP) has become more popular in recent years. By stacking different dies with different functions in a single package, SiP has benefits for space efficiency and flexibility of integrating functions. With die stacking, bi-material interfacial delamination becomes a prime concern of reliability testing. This paper presents an evaluation of molding compound and underfill material for wire bond stacked flip chip CSP (WBSFCCSP). The test vehicle size is 16mm × 16mm × 1.2mm with a 4mm × 5mm × 0.15mm low-K wire bond die stacked on a low-k 8mm × 8mmm × 0.15mm flip chip die. The reliability testing condition is JEDEC MSL2a (60°C/60%RH, 120hrs, reflow three times at peak temperature of 260°C) and 1000 cycles of thermal cycling test (TCT -55°C~125°C). The severe pre-conditioning environment makes the material selection become more challenging. Delamination between the underfill and other package components leads to premature failure. TCT stress also induces the interface of bottom die backside and encapsulated molding compound delamination. In this evaluation, the EMC selection was decided by the first stage experimental results based on the assembly yield. A design of experiments (DOE) performed by finite element analysis (FEA) was used to study the effect of underfill property on package stress. From FEA results, the underfill selection trend for solving underfill delamination and bottom die backside delamination is a conflict. Low coefficient of thermal expansion (CTE) and high Young's modulus (E) underfill can reduce the stress at bottom die backside corner but increase the underfill pressure. In order to solve this conflict, plasma cleaning was applied before underfill dispensing to improve the underfill and package components interface bond strength. In the second stage experiment, three underfills were evaluated base on different reasons, low modulus to prevent underfill delamination, high modulus to reduce bottom die backside stress and low moisture absorption to reduce steam pressure. Only the high modulus underfill can pass reliability testing.
机译:随着消费电子市场的消耗,近年来,包装系统(SIP)变得更加流行。通过在单个包装中堆叠不同功能的不同模具,SIP对空间效率和集成功能的灵活性具有好处。通过模具堆叠,双材料界面分层成为可靠性测试的主要关注点。本文介绍了用于堆叠倒装芯片CSP(WBSFCCSP)的线键合成型化合物和底部填充材料的评估。试验车辆尺寸为16mm×16mm×1.2mm,带4mm×5mm×0.15mm低k线键盘堆叠在低k 8mm×8mmm×0.15mm倒装芯片管芯上。可靠性测试条件是JEDEC MSL2A(60°C / 60%RH,120HR,峰值温度的30Hrs,在260°C的峰值温度下的三次,热循环测试1000个循环(TCT -55°C〜125°C)。严重的预处理环境使材料选择变得更具挑战性。底部填充物和其他包装部件之间的分层导致过早失效。 TCT应力还诱导底部管芯背面和封装的模塑复合分层的界面。在该评估中,EMC选择基于大会收益率的第一阶段实验结果决定。通过有限元分析(FEA)进行的实验(DOE)设计研究欠填充物质对包装应力的影响。从FEA结果中,解决欠填充分层和底部模位后分层的底部填充选择趋势是一种冲突。低热膨胀系数(CTE)和高杨氏模量(e)底部填充物可以减小底部模板后角处的应力,但增加了欠填充压力。为了解决这种冲突,在底部填充分配之前施加等离子体清洁,以改善底部填充和包装部件界面粘合强度。在第二阶段实验中,三种底部填充物以不同的原因评估基础,低模量以防止填充分层,高模量减少底部管芯背面应力和低湿吸收以降低蒸汽压力。只有高模量填充物可以通过可靠性测试。

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