Eight Bit Serial Triangular Compressor Based Multiplier

摘要

This paper proposes a novel and area efficient bit serial multiplier architecture in which both the multiplier and multiplicand are processed in real time. The major advantage of proposed multiplier is the bit serial data which results in reduced area and simple circuitry, the use of compressor enables us to get bit serial out put every clock cycle. The proposed architecture is best suited for bit serial communication system. The proposed bit serial multiplier is an integral part of bit serial digital down converter. The design uses a compressor algorithm for partial product addition which removes the dependency of each data bit from its previous one by using a triangular compressor. The complexity of our algorithm is 2n+1.