首页> 外国专利> Multiplier, especially a serial bit multiplier, free from internal overflow, and method for preventing internal overflow in a multiplier

Multiplier, especially a serial bit multiplier, free from internal overflow, and method for preventing internal overflow in a multiplier

机译:乘法器,特别是串行位乘法器,没有内部溢出,以及用于防止乘法器内部溢出的方法

摘要

A multiplier for least significant bit first multiplication of a multiplicand coded on n bits by a multiplier coefficient includes a processor which, for each bit of the decimal part of the multiplier coefficient between the least significant bit and the most significant bit, calculates the sum of rank n+1 obtained from partial products of the bit in question with the n bits of the multiplicand and from corresponding sums calculated for the preceding bit or bits of the multiplier coefficient. This prevents internal overflow of the multiplier.
机译:用于在n位上编码的被乘数的最低有效位优先乘以乘数系数的乘法器包括处理器,该处理器针对最低有效位和最高有效位之间的乘法系数的小数部分的每个位,计算从所讨论的位与被乘数的n位的乘积以及从为乘数系数的前一位或多位计算出的相应和获得的等级n + 1。这样可以防止乘法器内部溢出。

著录项

  • 公开/公告号US5511018A

    专利类型

  • 公开/公告日1996-04-23

    原文格式PDF

  • 申请/专利权人 FRANCE TELECOM;

    申请/专利号US19940239667

  • 发明设计人 FREDDY BALESTRO;ALAIN WITTMANN;

    申请日1994-05-09

  • 分类号G06F7/52;

  • 国家 US

  • 入库时间 2022-08-22 03:38:39

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