Chip Joining of High End Flip Chip Organic Packages - Interconnect Pitch Reduction Challenges

摘要

As the semiconductor technology nodes move to 45nm, 32nm and then 22nm, the question of fundamental limits to traditional transistor scaling becomes increasingly prevalent. Does this same concern transcend to the chip to substrate interconnect? With each node, and its corresponding increase in transistor density, interconnection density from chip to substrate must increase accordingly, hence driving down the size of each interconnection. On the other hand, the drive to designing more performance into each semiconductor device results in other aspects of the device that do not scale accordingly; for example current per interconnection and chip size. Moreover, material sets are not standing still - more fragile low K dielectrics, Pb-free solders and denser, more complex organic substrates all impose additional challenges to the chip-substrate interconnection. So it becomes incumbent upon those tasked with designing, manufacturing, and assuring the quality of packages with higher numbers of finer pitch/smaller interconnects to first determine the pinch points then explore innovations in either material sets or processes to best address such pinch points. This paper focuses upon the pinch points that finer pitch interconnections impose specifically upon the flip chip solder reflow join process. The role of this process, often termed the Chip Join process, is to not only form reliable solder joints between chip and substrate but to do so in a manner that does not adversely affect the integrity of the interconnect (including isolation between interconnects) nor the integrity of the semiconductor device itself. As such, several aspects must be examined when considering the impact imposed upon chip joining by increasingly finer pitches and, more importantly, the smaller interconnection sizes that these finer pitches drive. Of course, actual joint creation, which is driven by the ability of the chip bump to wet the substrate pad, is of paramount importance and shall be addressed in detail. However, other issues during chip joining, such as electrical shorting, or near shorting, between joints as well as stresses that the joining process imparts on the back end of line (BEOL) wiring layers of the chip, also become more critical with diminished interconnection pitches and joint sizes, and will therefore be addressed.