Three-Dimensional Simulation of Polysilicon Thin Film Transistors with Single-, Double- and Surrounding-Gate Structures

摘要

In this paper, a three-dimensional simulation of single-, double-, and surrounding-gate polysilicon thin film transistors (TFTs) is presented. Grain trap model is considered in the transport model. Calculations of the driving current, I_D-V_D and I_D-V_G curves are performed. Among three device structures, polysilicon TFTs with surrounding-gate structure reduce the leakage current and improve the short channel effects due to the excellent infinite-gate channel controllability.