Strain Relaxation in Strained-Si Layer on SiGe-on-Insulator Substrate

摘要

Strained SOI-MOSFETs are promising device structures for high-performance CMOS applications, because of their high current drive and low parasitic capacitances [1]. It has been demonstrated that uniform 150 and 200mm strained-Si/SGOI (SiGe-on-Insulator) wafers with the ULSI grade have been successfully fabricated by the Ge condensation process [2] to realize excellent device performances even for 35nm-gate-length MOSFETs [3, 4]. On the other hand, subthreshold characteristics of MOSFETs on the strained-SOI wafers were occasionally deteriorated by the presence of misfit dislocations at the Si/SiGe interface [4]. The critical thickness, h{sub}c, of strained-Si on SiGe alloy, therefore, is one of the most important parameters for strained-Si technologies. However, this thickness has not been well characterized yet. Our previous work confirmed that 90° partial dislocation glides and stacking faults are introduced into strained-Si layers during the mismatched growth of the tensile layers on (001) SGOI substrates [5]. In this work, in order to determine the h{sub}c of strained-Si layers and to examine the strain relaxation mechanism, a formation of misfit dislocations and dislocation morphology have been investigated for a wide range of the SiGe alloy compositions and strained-Si layer thicknesses. The strain relaxation occurs first through a formation of the misfit dislocation of 90° Shockley partials and sluggishly proceeds via a formation of 60°perfect dislocations with increasing thicknesses of the highly tensile mismatched Si. Also, the classical kinetic model based on the Dodson and Tsao approach [6] is found to provide partially successful agreement with the relaxation behavior and the values of h{sub}c, experimentally obtained in this work.