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EFFECTS OF MISALIGNMENT ON RELIABILITY OF FLIP CHIP SOLDER JOINTS USING FEA

机译:错位对使用FEA倒装芯片焊点可靠性的影响

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摘要

The effects of misalignment on a flip chip structure are studied with the finite element method (FEM) using three-dimensional (3-D) models. The accumulated plastic work on third temperature cycle in a corner bump is used to compare the reliabilities of structures with different misalignments. The results show that generally misalignment decreases the reliability of a flip chip package. However, unequal spacing of pads on chip and substrate can improve the reliability.
机译:使用三维(3-D)型号用有​​限元方法(FEM)研究了未对准对倒装芯片结构的影响。在角凸块中的第三温度循环上的累积塑性工作用于比较结构的可靠性与不同的错位。结果表明,通常的错位会降低倒装芯片封装的可靠性。然而,芯片和基材上的垫的不等间距可以提高可靠性。

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