The interconnect design and analysis of Rambus memory channel

摘要

This paper describes the interconnect design, modeling, and analysis of the Direct Rambus memory channel. A brief introduction of the Rambus channel architecture along with several design issues are presented. Due to the high bandwidth of Rambus channel, it is crucial to accurately model the frequency-varying nature of transmission lines. In the past, the interconnect extraction often involved many test structures and vector network analyzer (VNA) measurements. This paper presents a new approach that models an arbitrary structure by coupled transmission lines in cascade, and optimizes all RLGC matrices for the measured S parameters using only one short-circuit measurement. It is noted that a complex package, often modeled by many lumped elements, could be represented by a simple transmission line. The simulated waveforms were shown to correlate well with time-domain reflectometer (TDR) and scope measurements. Thousands of READ and WRITE simulations were performed using various patterns, configurations, and corner models to ensure a robust design with ample voltage and timing margins.