EEPROM cell with n-well and MIM capacitor is proposed and fabrication is done by using the 0.18μm standard CMOS process. Single polysilicon EEPROM cell applies the stacked metal-insulator-metal (MIM) or n-well capacitor to increase a memory capacity. Although MIM capacitor cell shows a good device performance, it requires a large device-size. N-well control gate cell has an inherent high junction capacitance and high sheet resistance. In this paper, we propose an EEPROM cell that has both MIM and n-well capacitor in order to achieve a small device size with an excellent programming characteristics. The cell does not require any additional cell area to obtain a high capacitance and has a good control gate coupling ratio with contribution of the junction capacitance between control gate and n-well. Because n-well depletion capacitor is isolated by shallow trench isolation (STI) and MIM capacitor is located just above the n-well capacitor, the cell with two parallel connected capacitors is expected to offer an excellent reliability and noise immunity.
展开▼
