Implications for Robust Reliability Testing of Power SiC MOSFETs

摘要

Threshold voltage (V_T) instability remains an important issue for the performance, reliability, and qualification of large-area SiC power MOSFET devices. The direct application of existing reliability test standards to SiC power MOSFETs can in some cases result in an inconsistent pass/fail response for a given device. Significant variations in the I_D-V_(GS) characteristics, with accompanying shift in V_T and change in leakage current, can result when these prescribed standards are applied as written. These variations are likely due to the complex time, temperature, and bias dependent nature of the charging and discharging of significant numbers of near-interfacial oxide traps that exists in as-processed SiC MOSFET devices. The significant increase in this V_T instability at elevated temperature may suggest the activation of additional performance limiting oxide defects. If the negative shift in V_T is large enough, it may increase the OFF-state drain leakage current and limit the long-term device reliability.