Though work on 3-d and later 2.5-d packaging has been going on now for over 5 years, we do not yet see large applications in areas other than traditional heterogeneous integration e, g. in camera modules. Adoption of 2.5-d Si interposer technology in 2010-11 to build FPGA modules on a commercial scale had generated much enthusiasm and expectation that floodgates will open for wide use of this technology e, g. in every Smart Phone but that has not yet materialized, giving rise to a shift in attention in Blogs and Conferences from purely digital applications e.g. processor - memory modules to more performance driven and cost insensitive applications e.g. heterogeneous modules for electro - optic I/O in servers etc. Roadmaps for emerging technologies like 3-d stacking or 2.5-d modules are developed taking process maturity into consideration but they must also anticipate major applications. Such applications using a new technology can succeed only if there are overwhelming advantages in performance and system cost that negate increases in module costs. When the author and his team developed electroplated solder bump flip chip technology and their high volume implementation at two of the leading IDMs over 2 decades ago, both performance (electrical) and cost modeling were used to short list applications most likely to succeed and limit process development only for those applications. Countless users & providers of flip chip technology since then have benefited from this original work on electroplated solder and pillar bumps as well as build up type organic substrate technologies. A similar theoretical approach is sorely needed in the development of 2.5-d and 3-d technologies to define the most cost - effective configurations and focus development work on only those. In this work we will discuss the Bandwidth and Power consumption (two of the key drivers for die stacking) of various 2.5-d and 3-d package configurations then compare them based on simulation results.
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