A New Fabrication Method for Multi-Layer Stacked Devices using Wafer-to-Wafer Stacked Technology based on 8-inch Wafers

摘要

This paper presents 3-layer stacked devices in which each wafer is stacked one after another, using 0.18μm CMOS technology based on 8-inch wafers. Electrical conductivity between each layer was almost 100% and interconnection resistance was less than 0.7Ω between the upper and lower wafers with a Buried Interconnection (BI) and a micro-bump. The prototype devices showed sophisticated functionality by testing, and the ratio of functional devices in the stacked wafer reached more than 60 percent