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Demonstration of phase-controlled Ni-FUSI CMOSFETs employing SiON dielectrics capped with sub-monolayer ALD HfSiON for low power applications

机译:采用SION电介质的相控Ni-Fusi CMOSFET的演示用亚单层ALD HFSION用于低功率应用

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In this work, by employing a sub-monolayer HfSiON cap (via ALD deposition) on the SiON host dielectrics in the phase-controlled Ni-FUSI CMOS devices, we report that 1) the devices (both n-FETs and p-FETs) V_t is effectively modulated likely due to the Fermi-level pinning relaxation; 2) the gate leakage is significantly reduced; 3) the dielectrics reliability characteristics (such as TZBD, pFETs NBTI, and nFETs PBTI) are clearly improved; 4) both the gate capacitance equivalent thickness (T_(inv)) and the long channel device high E_(eff) mobility are preserved. High-V-t ring oscillator with a delay of 17ps has been demonstrated, showing a much-reduced static power (~10 times) as compared to the devices using the pure SiON dielectrics. It is proposed that the SiON dielectrics capped with sub-monolayer HfSiON, in combination with the phase-controlled Ni-FUSI technology, is promising for 45nm and beyond low power CMOS applications.
机译:在这项工作中,通过在相位控制的Ni-Fusi CMOS器件中采用Sion主电介质上的子单层HFsion帽(通过ALD沉积),我们报告了1)设备(N-FET和P-FET) V_T由于FERMI-LEVEL PINNING SALLATION而有效地调节了可能的型号; 2)栅极泄漏显着降低; 3)显然改善了电介质可靠性特性(如TZBD,PFET NBTI和NFETS PBTI); 4)保留栅极电容等效厚度(T_(INV))和长通道设备高E_(EFF)移动性。已经证明了具有延迟17ps的高V-T环形振荡器,与使用纯SION电介质的器件相比,显示了静电功率(〜10倍)。建议用亚单层HFSION的SION电介质与相控的Ni-Fusi技术结合使用,是45nm及超出功率CMOS应用的45nm。

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